array multiplier
英 [əˈreɪ ˈmʌltɪplaɪə(r)]
美 [əˈreɪ ˈmʌltɪplaɪər]
网络 阵列乘法器; 组合阵列乘法器; 数组乘法器
双语例句
- Therefore, if each array element is8 bytes long, you can use8 as a multiplier.
因此，如果每个数组元素的长度都是8个字节，那么我们就可以使用8作为倍数。 - It is shown that this scheme has a higher speed and a small delay than the traditional CSA array multiplier.
优化下的并行乘法器比传统的CSA阵列乘法器速度快，且延时小。 - Self-scanned photodiode array multiplier traveling-wave photodiode
自扫描光电二极管阵 - Generalized Full Adder in Array Multiplier Design Model Application
一般化全加器在阵列乘法器设计中的典型应用 - A method of pre-distributing the calculated data by some additional judge logics is presented to optimize the power consumption of a pipelined array multiplier.
针对流水线结构阵列乘法器，分别采用寄存器翻转统计和门级翻转率统计的方法进行了功耗分析，创新地提出了一种通过增加判断逻辑进行数据预分流以实现功耗优化的方法。 - This paper introduces a new structure of numeral multilier: using one-level logic gate structure to realize array numeral multiplier, and using cmos technology to realize 8 × 8 ultraspeed array numeral multiplier with a new structure.
本文介绍了一种新的数码乘法器结构：采用一级逻辑门结构实现阵列式数码乘法器，并采用CMOS工艺技术实现新结构的8×8位超高速阵列式数码乘法器。 - After analyzing the classic 2-D and serial transportation systolic array architecture, a novel structure matrix multiplier based on 3-D square and serial-parallel mixed transportation was proposed.
在分析经典二维，串行心动结构矩阵乘法器的基础上，提出了基于三维的、串并行数据传输的新型结构。 - By analyzing the limitation of iterative cellular array multipliers, a parallel processing multiplier and its construction algorithm are presented in this paper.
在分析了叠接单元阵列乘法器的不足之处后，作者提出了并行处理乘法器的设想并提供了构造算法。 - Power Analysis and Optimization of a Pipelined Array Multiplier
流水线阵列乘法器的功耗分析和优化 - Abstract: This paper presents an automatic design method for a carry save array multiplier with arbitrary number of bits.
本文给出一种任意多位的保留进位阵列乘法器的自动设计方法。 - Analysis of a Carry Save Array Multiplier
一种保留进位阵列乘法器的分析 - Design of a 32-Bit Floating-Point Array Multiplier and a Comparison of Algorithms
32位浮点阵列乘法器的设计及算法比较 - After study a series array multipliers algorithms and architectures,. the author design a high-performance multiplier in logic gate level, which using Booth and Wallace skill.
本文研究讨论了各种不同阵列乘法器的结构和原理，并完成了在门电路级设计了32位基4Booth编码并采用42压缩的Wallace高性能阵列乘法器电路。 - This article starts from the 2 ′ s complement and the true value transformation relations, thoroughly analyzes the theory of four full adders, then directly proposes some schemes of the direct 2 ′ s complement array multiplier.
从补码和真值的转换关系开始，深入分析了四类全加器的工作原理，提出了直接补码阵列乘法器的设计方案。 - Array multiplier is one of the high_speed multipliers used in the high_speed computers, such as PENTIUM. This paper discusses the design and operation rules of the complement array multiplier.
阵列乘法器是在PENTIUM等高速计算机中采用的一种高速乘法运算器，据此讨论其补码阵列乘法器的设计和运算规则。 - Then a systolic array Multiplier is discussed. At last, structure of the 3D accelerating graphics engine is analyzed.
本文然后讨论了脉动矩阵乘法器的设计，最后讨论了3D几何图形加速引擎的结构。 - Secondly, systolic array Multiplier is designed which can speed up the multiplication of two matrices.
其次本文设计了脉动矩阵乘法器，用于加快两个矩阵的乘法运算。